SRAM devices are well-known and widely-used to store data in binary form (i.e., either the binary "0" or "1" logic states). In general, a static memory device is one which retains the stored binary logic state at all times when electrical power is applied to the device. Further, a randomly-accessible static memory device (i.e., an SRAM) is one that allows random access to any of the device's plurality of memory cells. Generally, the access time is the same for every cell in the device.
A well-known and widely-used single SRAM data storage cell is constructed from six metal oxide semiconductor ("MOS") transistors and two cross-coupled, inter-nodal resistors. This memory cell structure is duplicated literally thousands of times on a semiconductor IC substrate to form an SRAM device. A first pair of transistors form a first inverter, while a second pair of transistors form a second inverter. The output node of the first inverter is connected to the input node of the second inverter through a feedback resistor. Similarly, the output node of the second inverter is connected to the input node of the first inverter through a feedback resistor. The output node of each inverter is also connected to a corresponding pass or transfer transistor to connect that node to a bit line for selective reading and writing of the particular logic states currently stored in the memory cell. The two inverters, together with the feedback resistors, form a flip-flop circuit for storing data. One inverter stores either one of the two binary logic states, while the second inverter stores the opposite logic state.
The two feedback, cross-coupled or inter-nodal resistors are used to increase the resistive-capacitive ("RC") time delay which results from the inherent resistances and capacitances associated with, e.g., the routing lines and gate terminals of the inverter transistors. Generally, a relatively large RC time delay is desirable to prevent the SRAM memory cell from switching logic states when the cell is exposed to ionizing radiation. This could occur when the SRAM is utilized in a space or nuclear environment. However, the RC time delay cannot be so large as to unduly lengthen the time it takes to write data to the SRAM cell.
The ionizing radiation consists of charged particles which strike certain nodes (i.e., connection points) between the elements within the SRAM circuit. The generated electron/hole pairs can collect at a node in an amount that exceeds the critical amount of charge needed to keep the node at the currently-stored logic state. When excess charge is accumulated at, e.g., an output node of an inverter, charge can propagate to an input node of the opposite inverter. There, the charge can accumulate in an amount that can undesirably "upset" or switch the logic states currently stored in the SRAM memory cell. This inadvertent switching is referred to as a "single event upset" ("SEU") or a "soft error". The immunity of the SRAM memory cell to such errors is generally referred to as its "radiation hardness" capability or SEU immunity. The feedback resistors are typically a relatively high value (e.g., 250 k ohms), to limit the amount of charge that can undesirably propagate between nodes.
However, the use of such inter-nodal resistors in an SRAM cell is not without its drawbacks. Typically, the six transistors are fabricated in a first layer of polycrystalline silicon ("polysilicon") as part of the IC, while the two resistors are fabricated in a second polysilicon layer. See, for example, U.S. Pat. No. 5,135,882. This second layer of polysilicon adds considerable complexity to the IC processing steps in fabricating the SRAM device, along with topology problems in the resulting IC structure.
There are known prior art attempts at locating the six transistors and the two resistors of an SRAM memory cell within a single layer of polysilicon. See, for example, U.S. Pat. No. 5,126,279, which teaches the use of a salicide isolating mask layer to form the resistors and transistors in the same polysilicon layer. However, the single polysilicon layer approach has a number of manufacturability drawbacks, especially as device dimensions continually shrink in an attempt to achieve higher device integration levels. For example, one drawback is the reported inability to accurately control the grain-boundary-assisted diffusion between the heavily-doped transistor gate regions and the lightly-doped resistor regions within the single polysilicon layer. Any unwanted diffusion can significantly alter the sheet resistance of the resistor regions formed in the polysilicon layer. Another drawback is the reported inability to vary the thickness of the resistor region of the polysilicon layer independently of the gate region of the same polysilicon layer. See the aforementioned U.S. Pat. No. 5,135,882.
Regardless of whether or not the SRAM polysilicon resistors are formed in the same polysilicon layer as the transistors, there exists an inherent problem with resistors formed by polysilicon doping. Polysilicon resistors have relatively large voltage and temperature coefficients, which result in very large resistance values at low temperatures and small resistance values at high temperatures. Thus, at high SRAM device operating temperatures, the RC time delay may not be adequate enough to prevent soft errors. The typical solution is to increase the resistance values of the feedback resistors so that there exists a large enough RC time delay at high temperatures.
However, the downside to this approach is that there exists an even larger RC time delay at low temperatures, which could be excessive. An excessively large RC time delay can lead to unduly long time delays in writing data to the SRAM cell. In other words, a feedback resistor value adequate to provide SEU immunity at +125 degrees C will severely limit the speed in which SRAM cell may be written at -55 degrees C, thereby reducing the overall speed rating of the SRAM device.
One known attempted solution to the time delay problem associated with the memory write-in cycle is described and illustrated in U.S. Pat. No. 5,301,146 ("the '146 patent"). The '146 patent teaches the use of a transistor placed across a feedback resistor, together with added control logic for switching the transistor on and off. However, it should be noted that nowhere in the '146 patent is there mention of the feedback resistors being formed from polysilicon. As a result, nowhere in the '146 patent is there recognition of the aforementioned problem of the relatively large temperature coefficient of the polysilicon resistors. Instead, the underlying premise of the '146 patent is simply that the value of the feedback resistors, while large enough to provide adequate RC time delay, may be so large as to hinder the write-in speed of the SRAM cell. The '146 patent puts forth several related embodiments for selectively lowering the value of the feedback resistors during a memory cell write-in cycle. At all other times, the value of the feedback resistors is purportedly large enough to provide sufficient RC time delay and resulting immunity to soft errors.
In operation, all of the embodiments of the '146 patent are such that, when it is desired to write data to an SRAM cell, the added control logic turns on the transistor connected across the feedback resistor (or turns on the transistor acting as the feedback resistor itself). This lowers the effective value of the feedback resistance, thereby lowering the write-in time for the SRAM cell. During all other times, the added control logic keeps the transistor off. This keeps the feedback resistor at its high value, which insures an adequate RC time delay to prevent the occurrence of soft errors.
However, the obvious problem with the scheme described in U.S. Pat. No. 5,301,146 is space taken up by the added transistors and control logic. What is desired is simpler structural approach to selectively lowering the RC time delay during memory write cycles while keeping the RC time delay adequately high enough at all other times to provide sufficient protection against soft errors.